EP2S180F1508I4 Datasheet, PDF (71/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Stratix II Architecture
Figure 2–43 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLK pins. The connections to the global and
regional clocks from the top clock pins and enhanced PLL outputs is
shown in Table 2–11. The connections to the clocks from the bottom clock
pins is shown in Table 2–12.
Altera Corporation
May 2007
2–63
Stratix II Device Handbook, Volume 1