EP2S180F1508I4 Datasheet, PDF (112/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Document Revision History
Document
Table 2–27 shows the revision history for this chapter.
Revision History
Table 2–27. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v4.3 Updated “Clock Control Block” section.
—
Updated note in the “Clock Control Block” section.
—
Deleted Tables 2-11 and 2-12.
—
Updated notes to:
—
● Figure 2–41
● Figure 2–42
● Figure 2–43
● Figure 2–45
Updated notes to Table 2–18.
—
Moved Document Revision History to end of the chapter.
—
August 2006, Updated Table 2–18 with note.
—
v4.2
April 2006,
v4.1
● Updated Table 2–13.
● Removed Note 2 from Table 2–16.
● Updated “On-Chip Termination” section and Table 2–19 to
include parallel termination with calibration information.
● Added new “On-Chip Parallel Termination with Calibration”
section.
● Updated Figure 2–44.
● Added parallel on-
chip termination
description and
specification.
● Changed RCLK
names to match the
Quartus II software in
Table 2–13.
December
Updated “Clock Control Block” section.
—
2005, v4.0
July 2005, v3.1 ● Updated HyperTransport technology information in Table 2–18.
—
● Updated HyperTransport technology information in
Figure 2–57.
● Added information on the asynchronous clear signal.
May 2005, v3.0 ● Updated “Functional Description” section.
—
● Updated Table 2–3.
● Updated “Clock Control Block” section.
● Updated Tables 2–17 through 2–19.
● Updated Tables 2–20 through 2–22.
● Updated Figure 2–57.
March 2005, ● Updated “Functional Description” section.
—
2.1
● Updated Table 2–3.
2–104
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007