EP2S180F1508I4 Datasheet, PDF (230/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

External Memory Interface Specifications
External
Memory
Interface
Specifications
Tables 5–94 through 5–101 contain Stratix II device specifications for the
dedicated circuitry used for interfacing with external memory devices.
Table 5–94. DLL Frequency Range Specifications
Frequency Mode
0
1
2
3
Frequency Range
100 to 175
150 to 230
200 to 310
240 to 400 (–3 speed grade)
240 to 350 (–4 and –5 speed grades)
Resolution
(Degrees)
30
22.5
30
36
36
Table 5–95 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 5–95. DQS Delay Buffer Maximum Delay in Fast Timing Model
Frequency Mode
Maximum Delay Per Delay Buffer
(Fast Timing Model)
Unit
0
0.833
ns
1, 2, 3
0.416
ns
Table 5–96. DQS Period Jitter Specifications for DLL-Delayed Clock
(tDQS_JITTER) Note (1)
Number of DQS Delay Buffer
Stages (2)
1
2
3
4
Commercial
80
110
130
160
Industrial Unit
110
ps
130
ps
180
ps
210
ps
Notes to Table 5–96:
(1) Peak-to-peak period jitter on the phase shifted DQS clock.
(2) Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
5–94
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011