EP2S180F1508I4 Datasheet, PDF (118/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

SignalTap II Embedded Logic Analyzer
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For more information on JTAG, see the following documents:
■ The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II &
Stratix II GX Devices chapter of the Stratix II Device Handbook,
Volume 2 or the Stratix II GX Device Handbook, Volume 2
■ Jam Programming & Test Language Specification
SignalTap II
Embedded Logic
Analyzer
Stratix II devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA^®
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix II architecture are
configured with CMOS SRAM elements. Altera^® FPGA devices are
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Stratix II devices are configured at system power-up with data stored in
an Altera configuration device or provided by an external controller (e.g.,
a MAX^® II device or microprocessor). Stratix II devices can be configured
using the fast passive parallel (FPP), active serial (AS), passive serial (PS),
passive parallel asynchronous (PPA), and JTAG configuration schemes.
The Stratix II device’s optimized interface allows microprocessors to
configure it serially or in parallel, and synchronously or asynchronously.
The interface also enables microprocessors to treat Stratix II devices as
memory and configure them by writing to a virtual memory location,
making reconfiguration easy.
In addition to the number of configuration methods supported, Stratix II
devices also offer the design security, decompression, and remote system
upgrade features. The design security feature, using configuration
bitstream encryption and AES technology, provides a mechanism to
protect your designs. The decompression feature allows Stratix II FPGAs
to receive a compressed configuration bitstream and decompress this
data in real-time, reducing storage requirements and configuration time.
The remote system upgrade feature allows real-time system upgrades
from remote locations of your Stratix II designs. For more information,
see “Configuration Schemes” on page 3–7.
3–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007