EP2S180F1508I4 Datasheet, PDF (192/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Timing Model
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 3 of 3)
I/O Standard
Parameter
Minimum Timing
Industrial Commercial
-3 Speed
Grade
(2)
-3 Speed
Grade
(3)
-4 Speed
Grade
-5 Speed
Grade
Unit
1.2-V HSTL
t_{P I}
645
t_{P C O U T}
379
677
1194
1252
-
398
758
795
-
-
ps
-
ps
Notes for Table 5–73:
(1) These I/O standards are only supported on DQS pins.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–74. Stratix II I/O Input Delay for Row Pins (Part 1 of 2)
I/O Standard Parameter
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL
Class I
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
t_{P I}
t_{P C O U T}
Minimum Timing
Industrial Commercial
-3 Speed
Grade
(1)
-3 Speed
Grade
(2)
-4 Speed
Grade
-5 Speed
Grade
Unit
715
749
1287
1350
1477
1723 ps
391
410
760
798
873
1018 ps
726
761
1273
1335
1461
1704 ps
402
422
746
783
857
999
ps
788
827
1427
1497
1639
1911 ps
464
488
900
945
1035
1206 ps
792
830
1498
1571
1720
2006 ps
468
491
971
1019
1116
1301 ps
715
749
1287
1350
1477
1723 ps
391
410
760
798
873
1018 ps
547
573
879
921
1008
1176 ps
223
234
352
369
404
471
ps
547
573
879
921
1008
1176 ps
223
234
352
369
404
471
ps
577
605
960
1006
1101
1285 ps
253
266
433
454
497
580
ps
577
605
960
1006
1101
1285 ps
253
266
433
454
497
580
ps
602
631
1056
1107
1212
1413 ps
278
292
529
555
608
708
ps
5–56
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011