EP2S180F1508I4 Datasheet, PDF (228/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

PLL Timing Specifications
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
t_{L O C K}
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
t_{D L O C K}
Time required for the
PLL to lock
dynamically after
automatic clock
switchover between
two identical clock
frequencies
f_{S W I T C H OV E R}
Frequency range
4
where the clock
switchover performs
properly
f_{C L B W}
PLL closed-loop
0.13
bandwidth
f_{V C O}
PLL VCO operating 300
range for –3 and –4
speed grade devices
PLL VCO operating 300
range for –5 speed
grade devices
f_{S S}
Spread-spectrum
30
modulation frequency
% spread
Percent down spread 0.4
for a given clock
frequency
t_{P L L _ P S E R R}
Accuracy of PLL
phase shift
t_{A R E S E T}
Minimum pulse width 10
on areset signal.
t_{A R E S E T _ R E C O N F I G} Minimum pulse width 500
on the areset signal
when using PLL
reconfiguration. Reset
the PLL after
scandone goes
high.
Typ
0.03
1.20
0.5
Max
Unit
1
ms
1
ms
500
16.90
1,040
840
150
0.6
±15
MHz
MHz
MHz
MHz
kHz
%
ps
ns
ns
Notes to Table 5–92:
(1) Limited by I/O f_{M A X} . See Table 5–78 on page 5–69 for the maximum. Cannot exceed f_{O U T} specification.
(2) If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
5–92
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011