EP2S180F1508I4 Datasheet, PDF (153/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Bus Hold Specifications
Table 5–29 shows the Stratix II device family bus hold specifications.
Table 5–29. Bus Hold Parameters
Parameter Conditions
1.2 V
1.5 V
V_CCIO Level
1.8 V
2.5 V
3.3 V Unit
Min Max Min Max Min Max Min Max Min Max
Low
V_IN > V_IL
22.5
25.0
30.0
50.0
70.0
μA
sustaining (maximum)
current
High
V_IN < V_IH
–22.5
–25.0
–30.0
–50.0
–70.0
μA
sustaining (minimum)
current
Low
0 V < V_IN <
120
160
200
300
500 μA
overdrive V_CCIO
current
High
overdrive
current
0 V < V_IN <
V_CCIO
–120
–160
–200
–300
–500 μA
Bus-hold
trip point
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V
On-Chip Termination Specifications
Tables 5–30 and 5–31 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1), 2
Symbol
Description
Conditions
25-Ω R_S
3.3/2.5
Internal series termination with
calibration (25-Ω setting)
V_{C C I O} = 3.3/2.5 V
Internal series termination without V_{C CI O} = 3.3/2.5 V
calibration (25-Ω setting)
Resistance Tolerance
Commercial Industrial
Max
Max
Unit
±5
±10
%
±30
±30
%
Altera Corporation
April 2011
5–17
Stratix II Device Handbook, Volume 1