EP2S180F1508I4 Datasheet, PDF (104/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

High-Speed Differential I/O with DPA Support
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
TDI Input
Stratix II TDO V_{C C I O} Voltage Level in I/O Bank 4
Buffer Power _{VC C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V}
Non-Stratix II VCC = 3.3 V
v (1)
v (2)
v (3)
Level shifter Level shifter
required
required
VCC = 2.5 V v (1), (4)
v (2)
v (3)
Level shifter Level shifter
required
required
VCC = 1.8 V v (1), (4)
v (2), (5)
v
Level shifter Level shifter
required
required
VCC = 1.5 V v (1), (4)
v (2), (5)
v (6)
v
v
Notes to Table 2–20:
(1) The TDO output buffer meets V_OH (MIN) = 2.4 V.
(2) The TDO output buffer meets V_OH (MIN) = 2.0 V.
(3) An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
High-Speed
Differential I/O
with DPA
Support
Stratix II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1 Gbps. The LVDS and HyperTransport
differential I/O standards are supported in the Stratix II device. In
addition, the LVPECL I/O standard is supported on input and output
clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■ SPI-4 Phase 2 (POS-PHY Level 4)
■ SFI-4
■ Parallel RapidIO
■ HyperTransport technology
There are four dedicated high-speed PLLs in the EP2S15 to EP2S30
devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
Tables 2–21 through 2–26 show the number of channels that each fast PLL
can clock in each of the Stratix II devices. In Tables 2–21 through 2–26 the
first row for each transmitter or receiver provides the number of channels
driven directly by the PLL. The second row below it shows the maximum
channels a PLL can drive if cross bank channels are used from the
adjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15
2–96
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007