EP2S180F1508I4 Datasheet, PDF (169/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 6 of 6) Note (1)
Resources Used
Performance
Larger
designs
Applications
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, four
multipliers and two
adders FFT function
ALUTs
7385
6601
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
60
36 359.58
60
48 371.88
-3
Speed
Grade
(3)
352.98
355.74
-4
Speed
Grade
312.01
327.86
-5
Speed Unit
Grade
278.00 MHz
277.62 MHz
Notes for Table 5–36:
(1) These design performance numbers were obtained using the Quartus II software version 5.0 SP1.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) This application uses registered inputs and outputs.
(5) This application uses registered multiplier input and output stages within the DSP block.
(6) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
(7) This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
(8) This application uses the same clock source that is globally routed and connected to ports A and B.
(9) This application uses locally routed clocks or differently sourced clocks for ports A and B.
Altera Corporation
April 2011
5–33
Stratix II Device Handbook, Volume 1