EP2S180F1508I4 Datasheet, PDF (59/238 Pages) Altera Corporation – Section I. Stratix II Device Family Data Sheet

Figure 2–33. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
Stratix II Architecture
CLK[15..12]
CLK[3..0]
PLLs
CLK[7..4]
CLK[11..8] CLK[3..0]
PLLs
CLK[7..4]
CLK[11..8]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form busses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–34).
Figure 2–34. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Global Clock Network [15..0]
Clock [23..0]
Regional Clock Network [7..0]
Column I/O Cell
IO_CLK[7..0]
Lab Row Clock [5..0]
Row I/O Cell
IO_CLK[7..0]
Altera Corporation
May 2007
2–51
Stratix II Device Handbook, Volume 1