EP3C40F324C7N Datasheet, PDF (68/274 Pages) Altera Corporation – Chapter Revision Dates

5–8
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
clkena Signals
The Cyclone III device family supports clkena signals at the GCLK network level.
This allows you to gate-off the clock even when a PLL is used. Upon re-enabling the
output clock, the PLL does not need a resynchronization or re-lock period because the
circuit gates off the clock at the clock network level. In addition, the PLL can remain
locked independent of the clkena signals because the loop-related counters are not
affected.
Figure 5–4 shows how to implement the clkena signal.
Figure 5–4. clkena Implementation
clkena
clkin
DQ
clkena_out
clk_out
1 The clkena circuitry controlling the output C0 of the PLL to an output pin is
implemented with two registers instead of a single register, as shown in Figure 5–4.
Figure 5–5 shows the waveform example for a clock output enable. The clkena signal
is sampled on the falling edge of the clock (clkin).
1 This feature is useful for applications that require low power or sleep mode.
Figure 5–5. clkena Implementation: Output Enable
clkin
clkena
clk_out
The clkena signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during PLL resynchronization.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation