EP3C40F324C7N Datasheet, PDF (258/274 Pages) Altera Corporation – Chapter Revision Dates

11–6
Chapter 11: SEU Mitigation in the Cyclone III Device Family
Error Detection Timing
Table 11–5 lists the minimum and maximum error detection frequencies.
Table 11–5. Minimum and Maximum Error Detection Frequencies
Device Type
Cyclone III
device family
Error
Detection
Frequency
80 MHz/2ⁿ
Maximum Error
Detection
Frequency
80 MHz
Minimum Error
Detection
Frequency
312.5 kHz
Valid Divisors (2^)
0, 1, 2, 3, 4, 5, 6, 7, 8
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (for more information, refer to “Software Support” on page 11–7). The
divisor is a power of two (2), where n is between 0 and 8. The divisor ranges from one
through 256. Refer to Equation 11–1.
Equation 11–1. Error Detection Frequency
Error detection frequency = -⁸---⁰----^M------^H-----^z-
2ⁿ
CRC calculation time depends on the device and the error detection clock frequency.
Table 11–6 lists the estimated time for each CRC calculation with minimum and
maximum clock frequencies for Cyclone III device family.
Table 11–6. CRC Calculation Time
Device
Minimum Time (ms) ⁽¹⁾
Maximum Time (s)
(2)
EP3C5
5
2.29
EP3C10
5
2.29
EP3C16
7
3.17
EP3C25
9
4.51
Cyclone III
EP3C40
15
7.48
EP3C55
23
11.77
EP3C80
31
15.81
EP3C120
45
22.67
EP3CLS70
42
21.24
EP3CLS100
42
Cyclone III LS
EP3CLS150
79
21.24
40.27
EP3CLS200
79
40.27
Notes to Table 11–6:
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different
processes, voltages, and temperatures (PVT).
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation