EP3C40F324C7N Datasheet, PDF (173/274 Pages) Altera Corporation – Chapter Revision Dates

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–15
captures all its configuration data from the bitstream, it drives the nCEO pin low,
enabling the next device in the chain. You can leave the nCEO pin of the last device
unconnected or use it as a user I/O pin after configuration if the last device in the
chain is a Cyclone III device family. The nCONFIG, nSTATUS, CONF_DONE, DCLK, and
DATA[0] pins of each device in the chain are connected (Figure 9–4).
Figure 9–4. Multi-device AS Configuration
V_CCIO (1) V_CCIO (1) V_CCIO (1)
10 kΩ
10 kΩ
10 kΩ
V_CCIO (2)
10 kΩ
Serial Configuration
Device
DATA
DCLK
nCS
ASDI
25 Ω (6)
50 Ω (6), (8)
Master Device of the
Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA[0]
DCLK
nCSO (5)
ASDO (5)
MSEL[3..0]
50 Ω(8)
Buffers (7)
Slave Device of the Cyclone III Device Family
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C. (3)
DATA[0]
DCLK
(4)
MSEL[3..0]
(4)
Notes to Figure 9–4:
(1) Connect the pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of the I/O bank in which the nCE pin resides.
(3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device
family in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and slave devices in PS mode,
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or GND.
(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in other
AP and FPP modes.
(6) Connect the series resistor at the near end of the serial configuration device.
(7) Connect the repeater buffers between the master and slave devices of the Cyclone III device family for DATA[0] and DCLK. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in
“Configuration and JTAG Pin I/O Requirements” on page 9–7.
(8) The 50- series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series
resistors if the 2.5- or 3.0-V configuration voltage standard is applied.
The first Cyclone III device family in the chain is the configuration master and
controls the configuration of the entire chain. You must connect its MSEL pins to
select the AS configuration scheme. The remaining Cyclone III device family is
configuration slaves and you must connect their MSEL pins to select the PS
configuration scheme. Any other Altera device that supports PS configuration can
also be part of the chain as a configuration slave.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1