EP3C40F324C7N Datasheet, PDF (202/274 Pages) Altera Corporation – Chapter Revision Dates

9–44
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Cyclone III device family receives configuration data on the DATA[7..0] pins and the
clock is received on the DCLK pin. Data is latched into the device on the rising edge of
DCLK. Data is continuously clocked into the target device until CONF_DONE goes high.
The CONF_DONE pin goes high one byte early in FPP configuration mode. The last byte
is required for serial configuration (AS and PS) modes.
1 Two DCLK falling edges are required after CONF_DONE goes high to begin the
initialization of the device.
Supplying a clock on CLKUSR does not affect the configuration process. After the
CONF_DONE pin goes high, CLKUSR is enabled after the time specified as t_CD2CU. After
this time period elapses, Cyclone III device family requires certain amount of clock
cycles to initialize properly and enter user mode. For more information about the
initialization clock cycles required in the Cyclone III device family, refer to Table 9–5
on page 9–10. For more information about the supported CLKUSR f_MAX value for
Cyclone III device family, refer to Table 9–14 on page 9–47.
The INIT_DONE pin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure that DCLK and DATA[0] are not left floating at the end of the configuration,
the MAX II device must drive them either high or low, whichever is convenient on
your board. The DATA[0] pin is available as a user I/O pin after configuration. When
you choose the FPP scheme in the Quartus II software, the DATA[0] pin is tri-stated by
default in user mode and must be driven by the external host device. To change this
default option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device and Pin Options dialog box.
The DCLK speed must be below the specified system frequency to ensure correct
configuration. No maximum DCLK period exists, which means you can pause
configuration by halting DCLK for an indefinite amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUS after a reset time-out period (a maximum of 230 s). After nSTATUS is released
and pulled high by a pull-up resistor, the external host device can try to reconfigure
the target device without needing to pulse nCONFIG low. If this option is turned off, the
external host device must generate a low-to-high transition (with a low pulse of at
least 500 ns) on nCONFIG to restart the configuration process.
The external host device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The CONF_DONE pin must be monitored by the external device
to detect errors and to determine when programming is complete. If all configuration
data is sent but CONF_DONE or INIT_DONE has not gone high, the external device must
reconfigure the target device.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation