EP3C40F324C7N Datasheet, PDF (100/274 Pages) Altera Corporation – Chapter Revision Dates

6–2
Chapter 6: I/O Features in the Cyclone III Device Family
I/O Element Features
Figure 6–1 shows the Cyclone III device family IOE structure.
Figure 6–1. Cyclone III Device Family IOE in a Bidirectional I/O Configuration
io_clk[5..0]
Column
or Row
Interconnect
OE
clkout
oe_out
aclr/prn
Chip-Wide Reset
data_in1
data_in0
sclr/
preset
clkin
oe_in
OE Register
D
Q
ENA
ACLR
/PRN
V_CCIO
Optional
PCI Clamp
V_CCIO
Programmable
Pull-Up
Resistor
Output Register
D
Q
ENA
ACLR
/PRN
Output
Pin Delay
Current Strength Control
Open-Drain Out
Slew Rate Control
D
Q
ENA
ACLR
/PRN
Input Register
Input Pin to
Input Register
Delay
or Input Pin to
Logic Array
Delay
Bus Hold
I/O Element Features
The Cyclone III device family IOE offers a range of programmable features for an I/O
pin. These features increase the flexibility of I/O utilization and provide an
alternative to reduce the usage of external discrete components to on-chip, such as a
pull-up resistor and a diode.
Programmable Current Strength
The output buffer for each Cyclone III device family I/O pin has a programmable
current strength control for certain I/O standards.
The LVTTL, LVCMOS, SSTL-2 Class I and Class II, SSTL-18 Class I and Class II,
HSTL-18 Class I and Class II, HSTL-15 Class I and Class II, and HSTL-12 Class I
and Class II I/O standards have several levels of current strength that you can
control.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation