EP3C40F324C7N Datasheet, PDF (178/274 Pages) Altera Corporation – Chapter Revision Dates

9–20
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Altera recommends putting a buffer before the DATA and DCLK output from the master
device to avoid signal strength and integrity issues. The buffer must not significantly
change the DATA-to-DCLK relationships or delay them with respect to other AS signals
(ASDI and nCS). Also, the buffer must only drive the slave devices to ensure that the
timing between the master device and the serial configuration device is unaffected.
This configuration method supports both compressed and uncompressed .sofs.
Therefore, if the configuration bitstream size exceeds the capacity of a serial
configuration device, you can enable the compression feature in the .sof or you can
select a larger serial configuration device.
Guidelines for Connecting Serial Configuration Device to Cyclone III Device
Family on AS Interface
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Cyclone III device family must
follow the recommendations listed in Table 9–9.
Table 9–9. Maximum Trace Length and Loading for the AS Configuration
Cyclone III
Device Family
AS Pins
DCLK
DATA[0]
nCSO
ASDO
Maximum Board Trace Length from the
Cyclone III Device Family to the Serial
Configuration Device (Inches)
10
10
10
10
Maximum Board Load (pF)
15
30
30
30
Estimating AS Configuration Time
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Cyclone III device family. This serial interface is clocked
by the Cyclone III device family DCLK output (generated from an internal oscillator).
Equation 9–2 and Equation 9–3 show the configuration time estimation for the
Cyclone III device family.
Equation 9–2.
Size  _^m------^a---^x---ⁱ--^m-----^u----^m----₁--^D---_b--^C-_i--_t-^L----^K------^p---^e---^r---ⁱ-^o----^d--_ = estimated maximum configuration ti
Equation 9–3.
3,500,000
bits



5_-1---0_--b--n_-i--t-s_
=
175 ms
To estimate the typical configuration time, use the typical DCLK period shown in
Figure 9–7 on page 9–22. With a typical DCLK period of 33.33 ns, the typical
configuration time is 116.7 ms. Enabling compression reduces the amount of
configuration data that is sent to the Cyclone III device family, which also reduces
configuration time. On average, compression reduces configuration time by 50%.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation