EP3C40F324C7N Datasheet, PDF (154/274 Pages) Altera Corporation – Chapter Revision Dates

8–12
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
DDR Output Registers
A dedicated write DDIO block is implemented in the DDR output and output enable
paths. Figure 8–5 shows how Cyclone III device family dedicated write DDIO block is
implemented in the I/O element (IOE) registers.
Figure 8–5. Cyclone III Device Family Dedicated Write DDIO
Output Enable
DDR Output Enable Registers
IOE
Register
datain_l
datain_h
-90° Shifted Clock
Output Enable
Register A_OE
data1
data0
IOE
Register
Output Enable
Register B_OE
DDR Output Registers
IOE
Register
Output Register A_O
data0
data1
IOE
Register
®
Output Register B_O
DQ or DQS
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_l and datain_h, are fed into two registers,
output register Ao and output register Bo, respectively, on the same clock edge.
The output from output register Ao is captured on the falling edge of the clock, while
the output from output register Bo is captured on the rising edge of the clock. The
registered outputs are multiplexed by the common clock to drive the DDR output pin
at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQS write preamble time specification.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation