EP3C40F324C7N Datasheet, PDF (212/274 Pages) Altera Corporation – Chapter Revision Dates

9–54
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–27. JTAG Configuration of Multiple Devices Using a Download Cable (1.2, 1.5, and 1.8-V V_CCIO Powering the
JTAG Pins)
Download Cable
10-Pin Male Header
Pin 1
VCCIO (1) VCCIO(1)
Cyclone III
VCCIO(1)
(6)
VCCIO (5)
VCCIO (1)
(2)
(6)
(2)
10 kΩ Device Family
nSTATUS
DATA[0]
DCLK
10 kΩ
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
VIO
(3)
nCE (4)
VCCIO(1)
10 kΩ
Cyclone III
Device Family
VCCIO(1)
10 kΩ
VCCIO ⁽¹⁾
10 kΩ
Cyclone III
Device Family
VCCIO ⁽¹⁾
10 kΩ
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
nCE (4)
nSTATUS
(2)
DATA[0]
(2) DCLK
(2)
nCONFIG
(2)
MSEL[3..0] CONF_DONE
(2)
nCEO
nCE (4)
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
TDI
TMS
TCK
TDO
1 kΩ
Notes to Figure 9–27:
(1) Connect these pull-up resistors to the V_CCIO supply of the bank in which the pin resides.
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG configuration, connect the
nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and DATA[0] either high or low, whichever is convenient
on your board.
(3) In the USB-Blaster and ByteBlaster II cable, this pin is connected to nCE when it is used for AS programming, otherwise it is a no connect.
(4) The nCE pin must be connected to ground or driven low for successful JTAG configuration.
(5) Power up the V_CC of the ByteBlaster II or USB-Blaster cable with supply from V_CCIO. The ByteBlaster II and USB-Blaster cables do not support a
target supply voltage of 1.2 V. For the target supply voltage value, refer to the ByteBlaster II Download Cable User Guide and the USB-Blaster
Download Cable User Guide.
(6) The resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your setup.
1 All I/O inputs must maintain a maximum AC voltage of 4.1 V. If a non-Cyclone III
device family is cascaded in the JTAG-chain, TDO of the non-Cyclone III device family
driving into TDI of the Cyclone III device family must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
The nCE pin must be connected to GND or driven low during JTAG configuration. In
multi-device AS, AP, PS, and FPP configuration chains, the nCE pin of the first device
is connected to GND while its nCEO pin is connected to the nCE pin of the next device
in the chain. The inputs of the nCE pin of the last device come from the previous device
while its nCEO pin is left floating. In addition, the CONF_DONE and nSTATUS signals are
shared in multi-device AS, AP, PS, and FPP configuration chains to ensure that the
devices enter user mode at the same time after configuration is complete. When the
CONF_DONE and nSTATUS signals are shared among all the devices, every device must
be configured when you perform JTAG configuration.
If you only use JTAG configuration, Altera recommends that you connect the circuitry
as shown in Figure 9–26 or Figure 9–27, in which each of the CONF_DONE and nSTATUS
signals are isolated so that each device can enter user mode individually.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation