EP3C40F324C7N Datasheet, PDF (213/274 Pages) Altera Corporation – Chapter Revision Dates

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–55
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts the
second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure that the nCE pins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the configuration chain. As
long as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO pin of the previous device drives the nCE pin of the next
device low when it has successfully been JTAG configured. You can place other Altera
devices that have JTAG support in the same JTAG chain for device programming and
configuration.
1 JTAG configuration allows an unlimited number of Cyclone III device family to be
cascaded in a JTAG chain.
f For more information about configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains chapter in
volume 2 of the Configuration Handbook.
Figure 9–28 shows JTAG configuration of a Cyclone III device family with a
microprocessor.
Figure 9–28. JTAG Configuration of a Single Device Using a Microprocessor
Memory
ADDR DATA
Microprocessor
Cyclone III Device Family
nCE(3)
N.C.
(2)
(2)
(2)
nCEO MSEL[3..0]
nCONFIG
DATA[0]
DCLK
TDI (4)
TCK (4)
TDO
TMS (4) _nSTATUS
CONF_DONE
(2)
V_CCIO (1)
V_CCIO (1) _{10 kΩ}
10 kΩ
Notes to Figure 9–28:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain.
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a JTAG
configuration, connect the nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull DCLK and
DATA[0] either high or low, whichever is convenient on your board.
(3) The nCE pin must be connected to GND or driven low for successful JTAG configuration.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCK must fit the
maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
Configuring Cyclone III Device Family with Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard. The Jam Player
provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine.
f For more information about JTAG and Jam STAPL in embedded environments, refer
to AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To
download the jam player, visit the Altera website (www.altera.com).
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1