EP3C40F324C7N Datasheet, PDF (67/274 Pages) Altera Corporation – Chapter Revision Dates

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
5–7
Clock Networks
The inputs to the five clock control blocks on each side must be chosen from among
the following clock sources:
■ Four clock input pins
■ Five PLL counter outputs
■ Two DPCLK pins and two CDPCLK pins from both the left and right sides, and four
DPCLK pins and two CDPCLK pins from both the top and bottom
■ Five signals from internal logic
From the clock sources listed above, only two clock input pins, two PLL clock outputs,
one DPCLK or CDPCLK pin, and one source from internal logic can drive into any given
clock control block, as shown in Figure 5–1 on page 5–5.
Out of these five inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–3 shows a simplified version of the five clock control blocks on each side of
the Cyclone III device family periphery.
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family ⁽¹⁾
4
Clock Input Pins
PLL Outputs
5
2
CDPCLK
Clock
5
Control
2 or 4
Block
DPCLK
Internal Logic
5
GCLK
Five Clock Control
Blocks on Each Side
of the Device
Note to Figure 5–3:
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
GCLK Network Power Down
You can disable the Cyclone III device family GCLK (power down) by using both
static and dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable of the GCLKs in the Cyclone III device family.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page 5–5.
You can set the input clock sources and the clkena signals for the GCLK multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
f For more information, refer to the Clock Control Block (ALTCLKCTRL) Megafunction
User Guide.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1