EP3C40F324C7N Datasheet, PDF (196/274 Pages) Altera Corporation – Chapter Revision Dates

9–38
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Figure 9–16 shows a multi-device PS configuration when both Cyclone III device
family is receiving the same configuration data.
Figure 9–16. Multi-Device PS Configuration When Both Devices Receive the Same Data
Memory
V_CCIO (1) V_CCIO (1) _{Cyclone III Device Family}
ADDR DATA[0]
10 k 10 k
(3)
MSEL[3..0]
External Host
(MAX II Device or
Microprocessor)
GND
CONF_DONE
nSTATUS
nCE
nCEO
N.C. (2)
DATA[0] (4)
nCONFIG
DCLK (4)
Cyclone III Device Family
MSEL[3..0]
CONF_DONE
nSTATUS
nCE
nCEO
GND
DATA[0] (4)
nCONFIG
DCLK (4)
(3)
N.C. (2)
Buffers (4)
Notes to Figure 9–16:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. V_CC must be high enough to meet the V_IH specification of the I/O on the device and the external host.
(2) The nCEO pins of both devices are left unconnected or used as user I/O pins when configuring the same configuration
data into multiple devices.
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0],
refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to V_CCA or ground.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.
PS Configuration Timing
A PS configuration must meet the setup and hold timing parameters and the
maximum clock frequency. When using a microprocessor or another intelligent host
to control the PS interface, ensure that you meet these timing requirements.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation