EP3C40F324C7N Datasheet, PDF (130/274 Pages) Altera Corporation – Chapter Revision Dates

7–8
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Designing with LVDS
Cyclone III device family I/O banks support LVDS I/O standard. The left and right
I/O banks support true LVDS transmitters. On the top and bottom I/O banks, the
emulated LVDS transmitters are supported using two single-ended output buffers
with external resistors. One of the single-ended output buffers is programmed to have
opposite polarity. The LVDS receiver requires an external 100- termination resistor
between the two signals at the input buffer.
Figure 7–2 shows a point-to-point LVDS interface using Cyclone III device family true
LVDS output and input buffers.
Figure 7–2. Cyclone III Device Family LVDS Interface with True Output Buffer on the Left and Right I/O Banks
Transmitting Device
txout +
50 Ω
50 Ω
txout -
rxin +
100 Ω
rxin -
Cyclone III Device Family
Cyclone III
Device
Family Logic
Array
txout +
50 Ω
50 Ω
txout -
rxin +
Receiving Device
100 Ω
rxin -
Input Buffer
Output Buffer
Figure 7–3 shows a point-to-point LVDS interface with Cyclone III device family
LVDS using two single-ended output buffers and external resistors.
Figure 7–3. LVDS Interface with External Resistor Network on the Top and Bottom I/O Banks ⁽¹⁾
Cyclone III Device Family
Emulated
LVDS Transmitter
Resistor Network
RS
RP
RS
LVDS Receiver
50 Ω
50 Ω
100 Ω
Note to Figure 7–3:
(1) R_S = 120 ; R_P = 170 
BLVDS I/O Standard Support in the Cyclone III Device Family
The BLVDS I/O standard is a high-speed differential data transmission technology
that extends the benefits of standard point-to-point LVDS to multipoint configuration
that supports bidirectional half-duplex communication. BLVDS differs from standard
LVDS by providing a higher drive to achieve similar signal swings at the receiver
while loaded with two terminations at both ends of the bus.
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation