EP3C40F324C7N Datasheet, PDF (39/274 Pages) Altera Corporation – Chapter Revision Dates

Chapter 3: Memory Blocks in the Cyclone III Device Family
3–5
Overview
Figure 3–2. Cyclone III Device Family byteena Functional Waveform ⁽¹⁾
Note to Figure 3–2:
(1) For this functional waveform, New Data mode is selected.
When a byteena bit is deasserted during a write cycle, the old data in the memory
appears in the corresponding data-byte output. When a byteena bit is asserted during
a write cycle, the corresponding data-byte output depends on the setting chosen in
the Quartus^® II software. The setting can either be the newly written data or the old
data at that location.
Packed Mode Support
Cyclone III device family M9K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the following
conditions:
■ Each of the two independent block sizes is less than or equal to half of the M9K
block size. The maximum data width for each independent block is 18 bits wide.
■ Each of the single-port memory blocks is configured in single-clock mode. For
more information about packed mode support, refer to “Single-Port Mode” on
page 3–8 and “Single-Clock Mode” on page 3–15.
Address Clock Enable Support
Cyclone III device family M9K memory blocks support an active-low address clock
enable, which holds the previous address value for as long as the addressstall signal
is high (addressstall = '1'). When you configure M9K memory blocks in dual-port
mode, each port has its own independent address clock enable.
Figure 3–3 shows an address clock enable block diagram. The address register output
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram
address[0]
address[0]
register
address[0]
address[N]
addressstall
clock
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address[N]
register
address[N]
Cyclone III Device Handbook
Volume 1