AK4343VN Datasheet, PDF (98/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
վగཤྺ
Date
06/04/04
06/10/24
06/10/24
10/12/02
Revision
00
01
01
02
Reason
ॳ൛
࢓༷มߋ
هޡగਖ਼
هޡగਖ਼
هड़௥Ճ
Page Contents
35-36
53
65
75
87
88
91
94
ೖྗηϨΫλ
ʮࠩಈೖྗͰ࢖༻͢Δ৔߹ɺTable 20Ͱ “X”ҹͷ͍ͭ
͍ͯΔϐϯʹ͸৴߸Λೖྗ͠ͳ͍Ͱ͍ͩ͘͞ɻʯ௥
Ճɻ
Table 20(Handling of Line Input Pins)௥Ճɻ
εςϨΦϥΠϯग़ྗίϯτϩʔϧγʔέϯε
ύϫʔμ΢ϯઃఆ: PMLO bit = “1” Æ PMLO bit = “0”
I²CόείϯτϩʔϧϞʔυ
ʮ্Ґ3Ϗοτ͸ “0”ݻఆͰ͢ʯ Æ ʮ্Ґ2Ϗοτ͸
“0”ݻఆͰ͢ʯ
Ϩδελৄࡉઆ໌(Addr=0FH)
HPM bit: ʮHPM bit = “1”ͷͱ͖ɺ(L+R)/2ͷ৴߸͕ϔ
ουϑΥϯΞϯϓ͔Βग़ྗ͞Ε·͢ɻHPM bit = “1”
ͷͱ͖ɺPMHPL = PMHPR bits = “1”Ͱ࢖༻ͯ͠Լ͞
͍ɻʯ
ÆʮHPM bit = “1”ͷͱ͖ɺDACͷग़ྗ৴߸͸(L+R)/2
ͱͯ͠ϔουϑΥϯΞϯϓ͔Βग़ྗ͞Ε·͢ɻʯ
ίϯτϩʔϧγʔέϯε(Clock Setup: Ext Slave Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=27H Æ 00H
ίϯτϩʔϧγʔέϯε(Clock Setup: Ext Master Mode)
MCLK Frequency: 1024fs Æ 256fs
Addr=05H: Data=27H Æ 00H
ίϯτϩʔϧγʔέϯε(Headphone Playback)
Digital Volume Level: 0dB Æ −8dB
Addr=0EH: Data=14H Æ 19H
Figure 81: (12) Addr=0EH: Data=00H Æ 11H
ίϯτϩʔϧγʔέϯε(Clock Stop: PLL Master Mode)
MCKO bit = “H” or “L” Æ “1” or “0”
AK4343VNͷهड़Λ௥Ճ
MS0478-J-02
- 98 -
2010/11