AK4343VN Datasheet, PDF (52/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
■ εςϨΦϥΠϯग़ྗ (LOUT/ROUT pins)
DACL bitΛ “1”ʹ͢ΔͱɺDACͷLch, Rch৴߸ΛͦΕͧΕLOUT, ROUT pins͔ΒγϯάϧΤϯυͰग़ྗ͠·
͢ɻDACL bit Λ “0”ʹ͢Δͱɺग़ྗΛOFFʹ͢Δ͜ͱ΋ՄೳͰ͢ɻ͜ͷ࣌ɺLOUT, ROUT pins͸VCOMిѹ
Λग़ྗ͠·͢ɻ·ͨɺෛՙ఍߅͸min. 10kΩͰ͢ɻPMLO=LOPS bits = “0” ʹ͢Δͱɺύϫʔμ΢ϯঢ়ଶʹͳ
ΓAVSSʹ100kΩ(typ)Ͱϓϧμ΢ϯ͞Ε·͢ɻLOPS bit = “1”ͱ͢ΔͱɺύϫʔηʔϒϞʔυʹͳΓ·͢ɻ·
ͨɺLOPS bit = “1”ͱͯ͠ɺPMLO bitͰύϫʔμ΢ϯͷON/OFF Λߦ͏ͱɺON/OFF ࣌ʹൃੜ͢ΔϙοϓԻΛ
௿͢ݮΔ͜ͱ͕Ͱ͖·͢ɻ͜ͷͱ͖ɺFigure 42ʹࣔ͢Α͏ʹCΧοϓϧޙɺεςϨΦϥΠϯग़ྗͷϥΠϯΛ
20kΩͷ఍߅Ͱϓϧμ΢ϯ͍ͯͩ͘͠͞ɻ্ཱ͕ͪΓ͓ΑͼཱԼ͕Γͷ࣌ؒ͸C=1μF, AVDD=3.3Vͷͱ͖ɺ࠷
େ300msͰ͢ɻεςϨΦϥΠϯग़ྗ͸ɺPMLO bit = “1”͔ͭLOPS bit = “0”ͰύϫʔΞοϓঢ়ଶͱͳΓ·͢ɻ
εςϨΦϥΠϯग़ྗͷήΠϯ͸LOVL bitͰઃఆ͠·͢ɻ
DAC
“DACL”
“LOVL”
LOUT pin
ROUT pin
LOPS
0
1
Figure 41. εςϨΦϥΠϯग़ྗ
PMLO
Mode
LOUT/ROUT pin
0
ύϫʔμ΢ϯ
Pull-down to AVSS
1
௨ৗಈ࡞
௨ৗಈ࡞
0
ύϫʔηʔϒ
Fall down to AVSS
1
ύϫʔηʔϒ
Rise up to VCOM
Table 45. εςϨΦϥΠϯग़ྗͷϞʔυઃఆ (x: Don’t care)
(default)
LOVL
Gain
ग़ྗిѹ(typ)
0
0dB
0.6 x AVDD
(default)
1
+2dB
0.757 x AVDD
Table 46. εςϨΦϥΠϯग़ྗϘϦϡʔϜઃఆ
LOUT 1μF
ROUT
220Ω
20kΩ
Figure 42. εςϨΦϥΠϯग़ྗ֎෇͚ճ࿏(ϙοϓԻ௿ݮճ࿏࢖༻࣌)
MS0478-J-02
- 52 -
2010/11