AK4343VN Datasheet, PDF (13/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
DCಛੑ
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V)
Parameter
Symbol
min
typ
max
Units
High-Level Input Voltage
Low-Level Input Voltage
VIH 70%DVDD
-
-
V
VIL
-
-
30%DVDD V
High-Level Output Voltage
(Iout=−200μA) VOH DVDD−0.2
-
Low-Level Output Voltage
(Except SDA pin: Iout=200μA) VOL
-
-
(SDA pin: Iout=3mA) VOL
-
-
-
V
0.2
V
0.4
V
Input Leakage Current
Iin
-
-
±10
μA
εΠονϯάಛੑ
(Ta=25°C; AVDD=DVDD=2.6 ∼ 3.6V; HVDD=2.6 ∼ 5.25V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
Pulse Width Low
tCLKL 0.4/fCLK
-
-
Pulse Width High
tCLKH 0.4/fCLK
-
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
LRCK Output Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
fs
7.35
-
48
tLRCKH
-
tBCK
-
Duty
-
50
-
BICK Output Timing
Period
BCKO bit = “0”
BCKO bit = “1”
Duty Cycle
tBCK
-
1/(32fs)
-
tBCK
-
1/(64fs)
-
dBCK
-
50
-
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
Pulse Width Low
tCLKL 0.4/fCLK
-
-
Pulse Width High
tCLKH 0.4/fCLK
-
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
LRCK Input Timing
Frequency
DSP Mode: Pulse Width High
Except DSP Mode: Duty Cycle
BICK Input Timing
Period
Pulse Width Low
Pulse Width High
fs
tLRCKH
Duty
7.35
tBCK−60
45
tBCK
tBCKL
tBCKH
1/(64fs)
0.4 x tBCK
0.4 x tBCK
-
48
-
1/fs − tBCK
-
55
-
1/(32fs)
-
-
-
-
Units
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
%
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
ns
MS0478-J-02
- 13 -
2010/11