AK4343VN Datasheet, PDF (72/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
Addr
03H
Register Name
Signal Select 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
LOVL LOPS MGAIN1 SPKG1 SPKG0 MINL
0
0
0
0
0
0
0
0
0
0
MINL: εςϨΦϥΠϯग़ྗ ·ͨ͸ϨγʔόΞϯϓʹೖྗ͞ΕΔMIN৴߸ͷίϯτϩʔϧ
0: OFF (default)
1: ON
PMLO bit = “1”ͷ࣌ɺ͜ͷϏοτ͸༗ޮʹͳΓ·͢ɻPMLO bit = “0”ͷ࣌ɺLOUT, ROUT pins͸AVSS
Λग़ྗ͠·͢ɻ
SPKG1-0: εϐʔΧΞϯϓग़ྗήΠϯͷઃఆ(Table 53)
MGAIN1: ೖྗήΠϯίϯτϩʔϧ(Table 22)
LOPS: εςϨΦϥΠϯग़ྗͷύϫʔηʔϒϞʔυ
0: Normal Operation (default)
1: Power Save Mode
LOVL: εςϨΦϥΠϯ/Ϩγʔόग़ྗήΠϯઃఆ(Table 46, Table 47)
0: 0dB/+6dB (default)
1: +2dB/+8dB
Addr
04H
Register Name
Mode Control 1
Default
D7
D6
D5
D4
D3
D2
PLL3 PLL2 PLL1 PLL0 BCKO
0
0
0
0
0
0
0
DIF1-0: ΦʔσΟΦΠϯλϑΣʔεϑΥʔϚοτ (Table 17)
Default: “10” (લ٧Ί)
BCKO: ϚελϞʔυ࣌ͷBICKग़ྗप೾਺ͷઃఆ (Table 11)
PLL3-0: PLLج४ΫϩοΫͷબ୒ (Table 5)
Default: “0000”(LRCK pin)
D1
DIF1
1
D0
DIF0
0
Addr
05H
Register Name
Mode Control 2
Default
D7
D6
D5
D4
D3
D2
D1
D0
PS1
PS0
FS3
MSBS BCKP
FS2
FS1
FS0
0
0
0
0
0
0
0
0
FS3-0: αϯϓϦϯάप೾਺(See Table 6 and Table 7)ͼٴMCKIप೾਺ͷઃఆ(Table 12)
PLLϞʔυ࣌͸αϯϓϦϯάप೾਺ͷઃఆΛߦ͍ɺEXTϞʔυ࣌͸MCKIͷೖྗप೾਺Λઃఆ͠·
͢ɻ
BCKP: DSP Mode࣌ͷBICKۃੑઃఆ (Table 18)
“0”: “↑”ͰSDTOग़ྗ, “↓”ͰSDTIϥον (default)
“1”: “↓”ͰSDTOग़ྗ, “↑”ͰSDTIϥον
MSBS: DSP Mode࣌ͷLRCKҐ૬ઃఆ (Table 18)
“0”: LRCKͷ “↑”͕νϟωϧ੾ସͷBICK ൒पظલ (default)
“1”: LRCKͷ “↑”͕νϟωϧ੾ସͷBICK 1पظલ
PS1-0: MCKOप೾਺ͷઃఆ(Table 10)
Default: “00”(256fs)
MS0478-J-02
- 72 -
2010/11