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AK4343VN Datasheet, PDF (26/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP | |||
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[AK4343]
â PLLÍ·ÎϯϩοΫʹÍÍͯ
1) PLL Master Mode (AIN3 bit = â0â, PMPLL bit = â1â, M/S bit = â1â)
ÍÍ·ÏÊÏ
Í° PMPLL bit = â0â à â1âÞÍ¨Í Í´PLLÍϩοΫ͢ÎÎÍ°Í·ØɺBICKͱLRCK͸ âLâÎà¥à¾ÉºMCKO
bit = â1âͷͱÍMCKO pinÍÎ͸à©à§Í°Í³Íप೾਺ͷΫϩοΫÍà¥à¾ÍÎÎ͢ɻMCKO bit = â0âÍ·à§ß¹Í¸Éº
MCKO pin͸ âLâÎà¥à¾Í Î͢ɻ(Table 8)
PLLϩοΫÞɺBICKͱLRCKà¥à¾Í¸ âLâÍÎΫϩοΫà¥à¾Í±Í³ÎÎÍ¢É»à ·à¥³Í·1पظ෼ͷLRCK, BICK͸ɺà©
à§Í°Í³ÍÕà³³à©ÍÍÎÎÍ¢Íɺ1fsÍ´Þ͸à©à§Í³Î«Ï©Î¿Î«Í´Í³ÎÎ͢ɻ
αϯÏϦϯάप೾਺ÎมßÍ¢Îà§ß¹Í¸Ò°à±PMPLL bit = â0âÍ´Í¢ÎÍͱͰÎϯϩοΫà§à¬¶Í·à·à°Í³BICK,
LRCKÎà¥à¾Íͤͣʹ âLâÎà¥à¾ÍͤÎÍͱÍÍ°ÍÎ͢ɻ
PLL State
PMPLL bit â0â à â1âà¯Þ
MCKO pin
MCKO bit = â0â MCKO bit = â1â
âLâ Output
à·à°
BICK pin
âLâ Output
LRCK pin
âLâ Output
PLL Unlock à£(Ùà§ÒÖ)
âLâ Output
à·à°
à·à°
à·à°
PLL Lock à£
âLâ Output
See Table 10
See Table 11
1fs Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
2) PLL Slave Mode (AIN3 bit = â0â, PMPLL bit = â1â, M/S bit = â0â)
ÍÍ·ÏÊÏ
Ͱ͸ PMPLL bit = â0â à â1âÞÍ¨Í Í´PLLÍϩοΫ͢ÎÎÍ°Í·ØɺMCKOÍÎ͸à©à§Í°Í³Íप೾਺
ͷΫϩοΫÍà¥à¾ÍÎÎ͢ɻͦͷÞɺPLLÍϩοΫ͢ÎͱMCKO pinÍÎTable 10ͰબàÍÎͨΫϩοΫÍà¥
à¾ÍÎÎ͢ɻà Í ÉºPLLÍÎϯϩοΫʹͳͬͨà§ß¹ÉºDACÍÎ͸à©à§Í³ÏÊλÍà¥à¾ÍÎÎͤÎÉ»DACL,
DACH, DACS bitsÎ â0âÍ´Í¢ÎÍͱʹÎÎà¥à¾ÎÏÏ¡ÊÏÍ¢ÎÍͱÍÕೳͰ͢ɻ
PLL State
PMPLL bit â0â à â1âà¯Þ
MCKO pin
MCKO bit = â0â MCKO bit = â1â
âLâ Output
à·à°
PLL Unlock à£(Ùà§ÒÖ)
âLâ Output
à·à°
PLL Lock à£
âLâ Output
Output
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = â0â, M/S bit = â0â)
MS0478-J-02
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2010/11
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