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AK4343VN Datasheet, PDF (10/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP
◁
[AK4343]
Parameter
min
typ
max
Units
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, RL=8Ω, BTL,
HVDD=3.3V; unless otherwise specified.
Output Voltage (Note 17)
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
-
3.11
-
Vpp
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
3.13
3.92
4.71
Vpp
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
-
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
-
2.83
3.1
-
Vrms
-
Vrms
S/(N+D)
SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW)
-
60
-
dB
SPKG1-0 bits = “01”, −0.5dBFS (Po=240mW)
20
50
-
dB
HVDD=5V, SPKG1-0 bits = “11”, 0dBFS (Po=1W)
-
30
-
dB
Line Input Æ SPP/SPN pins, HVDD=5V,
SPKG1-0 bits = “11”, −1.5dBV Input (Po=1.2W)
-
20
-
dB
S/N (A-weighted)
80
90
-
dB
Load Resistance
8
-
-
Ω
Load Capacitance
-
-
30
pF
Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, AVOL=0dB, DVOL=0dB, CL=3μF, Rseries=10Ω x
2, BTL, HVDD=5.0V; unless otherwise specified.
Output Voltage SPKG1-0 bits = “10”, 0dBFS
-
6.75
-
Vpp
(Note 17) SPKG1-0 bits = “11”, 0dBFS
6.80
8.50
10.20
Vpp
S/(N+D)
SPKG1-0 bits = “10”, 0dBFS
-
60
-
dB
(Note 18) SPKG1-0 bits = “11”, 0dBFS
40
50
-
dB
S/N (A-weighted)
80
90
-
dB
Load Impedance (Note 19)
50
-
-
Ω
Load Capacitance (Note 19)
-
-
3
μF
Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ)
Maximum Input Voltage (Note 20)
-
1.98
-
Vpp
Gain (Note 21)
MIN Æ LOUT/ROUT LOVL bit = “0”
−4.5
0
+4.5
dB
LOVL bit = “1”
-
+2
-
dB
MIN Æ HPL/HPR
HPG bit = “0”
−24.5
−20
−15.5
dB
HPG bit = “1”
-
−16.4
-
dB
MIN Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
−0.07
+4.43
+8.93
dB
ALC bit = “0”, SPKG1-0 bits = “01”
-
+6.43
-
dB
ALC bit = “0”, SPKG1-0 bits = “10”
-
+10.65
-
dB
ALC bit = “0”, SPKG1-0 bits = “11”
-
+12.65
-
dB
ALC bit = “1”, SPKG1-0 bits = “00”
-
+6.43
-
dB
ALC bit = “1”, SPKG1-0 bits = “01”
-
+8.43
-
dB
ALC bit = “1”, SPKG1-0 bits = “10”
-
+12.65
-
dB
ALC bit = “1”, SPKG1-0 bits = “11”
-
+14.65
-
dB
Note 17. ग़ྗిѹ͸AVDDʹൺྫ͠·͢ɻ
Full-differentialͷ৔߹ɺVout = (SPP) − (SPN) = 0.94 x AVDD(typ)@SPKG1-0 bits = “00”, 1.19 x
AVDD(typ)@SPKG1-0 bits = “01”, 2.05 x AVDD(typ)@SPKG1-0 bits = “10”, 2.58 x AVDD(typ)@SPKG1-0
bits = “11”Ͱ͢ɻ
Note 18. ଌఆ఺͸SPP/SPN pinsͰ͢ɻ
Note 19. Figure 58ʹ͓͍ͯɺLoad Impedance͸γϦʔζ఍߅(Rseries)ͱ1kHzʹ͓͚ΔѹిεϐʔΧͷΠϯϐʔμ
ϯεͷ߹੒ΠϯϐʔμϯεͰ͢ɻLoad Capacitance͸ѹిεϐʔΧͷ༰ྔ੒෼Ͱ͢ɻѹిεϐʔΧΛ
࢖༻͢Δ৔߹ɺSPP, SPN pinʹͦΕͧΕ10ΩҎ্ͷγϦʔζ఍߅Λ઀ଓͯ͠Լ͍͞ɻ
Note 20. ࠷େೖྗిѹ͸AVDDͱ֎෦ೖྗ఍߅(Rin)ʹൺྫ͠·͢ɻVin = 0.6 x AVDD x Rin / 20kΩ (typ).
Note 21. ήΠϯ͸֎෦ೖྗ఍߅ʹ൓ൺྫ͠·͢ɻ
MS0478-J-02
- 10 -
2010/11
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