AK4343VN Datasheet, PDF (92/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
■ εςϨΦϥΠϯग़ྗ
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
(1)
DACL bit
(2)
(Addr:02H, D4)
1,111
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
Digital Volume: −8dB
LOVL=MINL bits = “0”
(10)
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
LOPS bit
(Addr:03H, D6)
PMDAC bit
(Addr:00H, D2)
E1H
18H
(3)
(4)
(5)
91H
28H
(7)
(8)
(3) Addr:09H&0CH, Data:91H
(4) Addr:0AH&0DH, Data:28H
(5) Addr:03H, Data:40H
(6) Addr:00H, Data:6CH
(11)
(7) Addr:03H, Data:00H
Playback
PMMIN bit
(Addr:00H, D5)
PMLO bit
(Addr:00H, D3)
LOUT pin
ROUT pin
(6)
>300 ms
(9)
Normal Output
>300 ms
(8) Addr:03H, Data:40H
(9) Addr:00H, Data:40H
(10) Addr:02H, Data:00H
(11) Addr:03H, Data:00H
Figure 82. Stereo Lineout Sequence
<खॱྫ>
ʮΫϩοΫͷઃఆʯͷ߲Λࢀর͠ɺΫϩοΫΛͯ͠څڙԼ͍͞ɻ
(1) αϯϓϦϯάप೾਺(FS3-0 bits)Λઃఆͯ͠Լ͍͞ɻPLLϞʔυͷ৔߹ɺαϯϓϦϯάप೾਺Λมߋ
͔ͯ͠ΒͷPLLϩοΫ࣌ؒΛߟྀ͠ɺ(5)ͷDACͼٴεϐʔΧͷύϫʔΞοϓΛߦͬͯԼ͍͞ɻ
(2) DAC Æ εςϨΦϥΠϯग़ྗͷύεͷઃఆ: DACL bit = “0” Æ “1”
(3) ALC෦σΟδλϧϘϦϡʔϜ(ΞυϨε09H&0CH)ͷઃఆ
AVL7-0 = AVR7-0 bits = “91H”(0dB)ʹઃఆͯ͠Լ͍͞ɻ
(4) ग़ྗσΟδλϧϘϦϡʔϜ(ΞυϨε0AH&0DH)ͷઃఆɻ
DVOLC bit = “1”(default)ͷͱ͖ɺDVL7-0bits(0AH)ͰLch͓ΑͼRchͷ྆ํͷϘϦϡʔϜΛઃఆ͠·
͢ɻDAC͕ύϫʔΞοϓ͞ΕͨޙɺDefault஋(0dB)͔Βઃఆͨ͠஋ʹιϑτભҠ͍͖ͯ͠·͢ɻ
(5) εςϨΦϥΠϯग़ྗΛύϫʔηʔϒϞʔυ΁Ҡߦ: LOPS bit = “0” Æ “1”
(6) DAC, MIN-AmpͼٴεςϨΦϥΠϯग़ྗͷύϫʔΞοϓ : PMDAC = PMMIN = PMLO bits = “0” → “1”
ظॳԽαΠΫϧத(1059/fs=24ms@fs=44.1kHz)ɺDACೖྗσʔλ͸಺෦Ͱ2’sίϯϓϦϝϯτͷ “0”
ݻʹఆ͞Ε·͢ɻॳظԽαΠΫϧ͕ऴྃ͢ΔͱɺDACͷ܈஗Ԇ(25/fs=0.5ms@fs=44.1kHz)ܦաޙɺ
DACग़ྗ͸σΟδλϧೖྗ৴߸ʹ૬౰͢ΔిѹʹͳΓ·͢ɻALC bit = “1”ͷ৔߹ɺॳظԽαΠΫϧ
த(1059/fs = 24ms @fs=44.1kHz)ɺALC͸σΟηʔϒϧঢ়ଶ(ALCͷήΠϯ͸AVL/R7-0 bitsͷઃఆ)Ͱɺ
ظॳԽαΠΫϧ͕ऴྃ͢ΔͱALC͸AVL/R7-0 bitsͷઃఆ͔Βಈ࡞Λ։࢝͠·͢ɻ
PMLO bit = “1”ͰLOUT, ROUT pins্ཱ͕͕ͪΓ࢝Ί·͢ɻ্ཱ͕ͪΓ࣌ؒ͸C = 1μF, AVDD=3.3V
ͷͱ͖max. 300msͰ͢ɻ
(7) εςϨΦϥΠϯग़ྗͷύϫʔηʔϒϞʔυͷղআ: LOPS bit = “1” Æ “0”
LOUT, ROUT pinsޙ্ཱ͕͕ͨͬͪɺઃఆΛߦ͍ͬͯͩ͘͞ɻઃఆޙɺLOUT, ROUT pins͔ΒͷԻ
੠ग़ྗ͕։࢝͞Ε·͢ɻ
(8) εςϨΦϥΠϯग़ྗΛύϫʔηʔϒϞʔυ΁Ҡߦ: LOPS bit: “0” Æ “1”
(9) DAC, MIN-AmpͼٴεςϨΦϥΠϯग़ྗͷύϫʔμ΢ϯ: PMDAC = PMMIN = PMLO bits = “1” → “0”
LOUT, ROUT pinsཱ͕ͪԼ͕Γ࢝Ί·͢ɻཱͪԼ͕Γ࣌ؒ͸C = 1μF, AVDD=3.3Vͷͱ͖max. 300ms
Ͱ͢ɻ
(10) DAC Æ εςϨΦϥΠϯग़ྗͷύεͷDisable: DACL bit = “1” Æ “0”
(11) εςϨΦϥΠϯग़ྗͷύϫʔηʔϒϞʔυͷղআ: LOPS bit = “1” Æ “0”
LOUT, ROUT pinsཱ͕ͪԼ͕ͬͨޙɺઃఆΛߦ͍ͬͯͩ͘͞ɻ
MS0478-J-02
- 92 -
2010/11