AK4343VN Datasheet, PDF (94/99 Pages) Asahi Kasei Microsystems – Stereo DAC with HP/RCV/SPK-AMP

[AK4343]
■ ΫϩοΫͷఀࢭ
DACΛ࢖༻͠ͳ͍৔߹͸ɺϚελΫϩοΫΛఀࢭ͢Δ͜ͱ͕Ͱ͖·͢ɻ
1. PLLϚελϞʔυͷ৔߹
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"1" or "0"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
Figure 84. Clock Stopping Sequence (1)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
(2) MCKOग़ྗͷఀࢭ: MCKO bit = “1” → “0”
(3) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
2. PLLεϨʔϒϞʔυ(LRCK, BICK pin)ͷ৔߹
PMPLL bit
(Addr:01H, D0)
External BICK
External LRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 85. Clock Stopping Sequence (2)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
(2) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
3. PLLεϨʔϒϞʔυ(MCKI pin)ͷ৔߹
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
(1)
(1)
(2)
Input
Example
Audio I/F Format: MSB justified
PLL Reference clock: MCKI
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 86. Clock Stopping Sequence (3)
<खॱྫ>
(1) PLLͷύϫʔμ΢ϯ: PMPLL bit = “1” → “0”
MCKOग़ྗͷఀࢭ: MCKO bit = “1” → “0”
(2) ֎෦ΫϩοΫΛࢭΊͯԼ͍͞ɻ
MS0478-J-02
- 94 -
2010/11