AKD4955-A Datasheet, PDF (9/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

[AKD4955-A]
(b) PLL Reference Clock: BICK pin
Registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: BICK pin).
AK4955
MCKO
MCKI
BICK
LRCK
SDTO
SDTI
DSP or μP
32fs, 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 14.PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX) and PORT2 (TOTX).
BICK, LRCK and SDTI are input from PORT3 (DSP). SDTO of the AK4955 is output to the PORT3
(DSP).
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
JP15
SDTI-SEL
JP16
MCKI-SEL
4
8
5
5
5
4
6
26
28
5
Figure 15.Setting of jumper pins with PLL Slave Mode (Note 5)
Note 5.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
<KM104703>
-9-
2011/08