AKD4955-A Datasheet, PDF (12/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

[AKD4955-A]
(4-3) Setting with PLL Slave Mode.
SW4 (M/S) should be set to “ON (H)”.
(a) PLL Reference Clock: MCKI pin
J10 (EXT) is used (Note 11). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT). BICK and LRCK are generated by using on-board divider and MCKO of
the AK4955. SDTI is connected to SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: MCKI pin).
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
JP15
SDTI-SEL
JP16
MCKI-SEL
4
8
5
5
5
4
6
26
28
5
JP17
4040-SEL
JP18
EXT
Figure 20.Setting of jumper pins with PLL Slave Mode (Note 12, Note 13)
Note 11.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
Note 12.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
Note 13.When BICK of 32fs is used, JP11 (BICK-SEL) should be set to “4040-32fs” side.
(b) PLL Reference Clock: BICK pin
PORT3 (DSP) is used. Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and J10 (EXT).
BICK and LRCK are generated by on-board divider which used MCLK from PORT3 (DSP). SDTI is
connected to SDTO of the AK4955 as loopback.
In addition, registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: BICKI pin).
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
4
8
5
5
6
2
JP14
MCKIO
JP15
SDTI-SEL
JP16
MCKI-SEL
5
4
6
28
5
JP17
4040-SEL
Figure 21.Setting of jumper pins with PLL Slave Mode (Note 14, Note 15)
Note 14.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
Note 15.When BICK of 32fs is used, JP11(BICK-SEL) should be set to “4040-32fs” side.
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2011/08