AKD4955-A Datasheet, PDF (10/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

[AKD4955-A]
(3-4) Setting with PLL Master Mode
The master clock is input from MCKI pin of J10 (EXT). An internal PLL circuit generates MCKO, BICK,
and LRCK.
In addition, registers of the AK4955 should be set to “PLL Master Mode”.
SW4 (M/S) should be set to “ON (H)”.
AK4955
11.2896MHz, 12MHz, 13.5MHz
24MHz, 25MHz, 27MHz
DSP or μP
MCKI
MCKO
B IC K
LRCK
SDTO
SDTI
256fs/128fs/64fs /32fs
32fs, 64fs
1f s
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 16.PLL Master Mode
J10 (EXT) and PORT3 (DSP) are used (Note 6). Nothing should be connected to PORT1 (TORX) and
PORT2 (TOTX).
MCKI is input from J10 (EXT) and SDTI is input from PORT3 (DSP). BICK, LRCK, MCKO and SDTO of
the AK4955 are output to the PORT3 (DSP).
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
4
8
5
5
6
2
JP1４
ＭＣＫＩＯ
JP15
SDTI-SEL
JP16
MCKI-SEL
JP18
EXT
5
4
6
28
5
Figure 17.Setting of jumper pins with PLL Slave Mode
Note 6.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
<KM104703>
- 10 -
2011/08