AKD4955-A Datasheet, PDF(11/89 Page) Asahi Kasei Microsystems

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AKD4955-A Datasheet, PDF (11/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

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[AKD4955-A]

(4) Evaluation of external Loop-back (A/D -> D/A).

(4-1) Setting with External Slave Mode.

J10 (EXT) is used (Note 7). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3

(DSP).

MCKI is input from J10 (EXT). BICK and LRCK are generated by on-board divider. SDTI is connected to

SDTO of the AK4955 as loopback.

In addition, registers of the AK4955 should be set to âExternal Slave Modeâ.

SW4 (M/S) should be set to âON (H)â.

JP11

BICK-SEL

JP12

JP13

BICK-PHASE LRCK-SEL

JP15

SDTI-SEL

JP16

MCKI-SEL

JP17

4040-SEL

JP18

EXT

Figure 18.Setting of jumper pins with External Slave Mode (Note 8, Note 9)

Note 7.When a termination (51â¦) of J10 (EXT) is not used, JP18 (EXT) should be open.

Note 8.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, âTHRâ or âINVâ

should be selected according to the Audio I/F format.

Note 9.When BICK of 32fs is used, JP11 (BICK-SEL) should be set to â4040-32fsâ side.

(4-2) Setting with External Master Mode.

J10 (EXT) is used (Note 10). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3

(DSP).

MCKI is input from J10 (EXT), SDTI is connected to SDTO of the AK4955 as loopback.

In addition, registers of the AK4955 should be set to âExternal Master Modeâ.

SW4 (M/S) should be set to âOFF (L)â.