AKD4955-A Datasheet, PDF (8/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

[AKD4955-A]
(3-3) Setting with PLL Slave Mode
A reference clock of PLL is selected among the input clocks supplied to MCKI pin. The required clock to
the AK4955 is generated by an internal PLL circuit.
SW4 (M/S) should be set to “ON (H)”.
(a) PLL Reference Clock: MCKI pin
Registers of the AK4955 should be set to “PLL Slave Mode” (Reference Clock: MCKI pin).
BICK and LRCK inputs should be synchronized with MCKO output. However the phase between
MCKO and LRCK dose not matter.
AK4955
11.2896MHz, 12MHz, 13.5MHz
24MHz, 25MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1f s
MCLK
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 12.PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
J10 (EXT) and PORT3 (DSP) are used (Note 3). Nothing should be connected to PORT1 (TORX) and
PORT2 (TOTX).
MCKI is input from J10 (EXT). BICK, LRCK and SDTI are input from PORT3 (DSP). MCKO and
SDTO of the AK4955 is output to the PORT3 (DSP).
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
4
8
5
5
6
2
JP1４
ＭＣＫＩＯ
JP15
SDTI-SEL
JP16
MCKI-SEL
JP18
EXT
5
4
6
28
5
Figure 13.Setting of jumper pins with PLL Slave Mode (Note 4)
Note 3.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
Note 4.JP12 (BICK-PHASE) is jumper which decides polarity of BICK, “THR” or “INV”
should be selected according to the Audio I/F format.
<KM104703>
-8-
2011/08