AKD4955-A Datasheet, PDF (13/89 Pages) Asahi Kasei Microsystems – AK4955 Evaluation Board Rev.3

[AKD4955-A]
(4-4) Setting with PLL Master Mode.
J10 (EXT) is used (Note 16). Nothing should be connected to PORT1 (TORX), PORT2 (TOTX) and PORT3
(DSP).
MCKI is input from J10 (EXT), SDTI is connected to SDTO of the AK4955 as loopback.
SW4 (M/S) should be set to “OFF (L)”.
JP11
BICK-SEL
JP12
JP13
BICK-PHASE LRCK-SEL
JP15
SDTI-SEL
JP16
MCKI-SEL
4
8
5
5
5
4
6
26
28
5
JP17
4040-SEL
JP18
EXT
Figure 22.Setting of jumper pins with PLL Master Mode
Note 16.When a termination (51Ω) of J10 (EXT) is not used, JP18 (EXT) should be open.
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2011/08