AKD4122A-A Datasheet, PDF (9/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
2. All clocks are fed through the 10pin port
When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2)
should be short. MCLK is supplied to the AK4122A, and the DATA that synchronizes with BICK and LRCK
output from the AK4122A is supplied to the AK4122A.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
(2-3) SW1 setting
Set SW1 according to the mode of the AK4122A PORT2.
SW1 No.
1
2
3
Name
M/S2
M/S3
TST4
ON (“H”)
OFF (“L”)
Master Mode
Slave Mode
Master Mode
Slave Mode
Fixed to “L”
Table 10. SW1 setting
Default
L
L
L
<KM099400>
-9-
2009/03