AKD4122A-A Datasheet, PDF (14/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2) and PORT8 (DIT2). MCLK is
input from J2 (EXT2), BICK LRCK, and DATA are supplied from the AK4122A. Set JP18 (MCLK2) to the
“EXT” in order to supply MCLK to the AK4122A.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• Clock Setting
MCLK is input from J2 (EXT2). JP7 (EXT2) should be open.
JP4
DIV2
JP5
CLK2
JP6
BCFS
JP7
EXT2
256 384 64fs 32fs
3. All clocks are fed through the 10pin port
When using PORT7 (DSP2), nothing should be connected to J2 (EXT2), PORT6 (DIR2) and PORT8 (DIT2).
JP7 (EXT2) should be short. MCLK is supplied to the AK4122A, and BICK, LRCK and DATA are supplied
from the AK4122A.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
(4-3) SW1 setting
Set SW1 according to the mode of the AK4122A PORT2.
SW1 No.
1
2
3
Name
M/S2
M/S3
TST4
ON (“H”)
OFF (“L”)
Master Mode
Slave Mode
Master Mode
Slave Mode
Fixed to “L”
Table 18. SW1 setting
Default
L
L
L
<KM099400>
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2009/03