AKD4122A-A Datasheet, PDF (12/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT7 (DSP2), nothing should be connected to PORT6 (DIR2). MCLK is input from J2 (EXT2),
BICK and LRCK are supplied by using the clock dividing circuit on this evaluation board to the AK4122A. Set
JP18 (MCLK2) to the “EXT” when MCLK is supplied to the AK4122A.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• Clock Setting
MCLK is input from J2 (EXT2), BICK and LRCK are generated by using the clock dividing circuit. JP4
(DIV2) and JP5 (CLK2) are set by referring to Table 14. JP6 (BCFS) selects the frequency of BICK. JP7
(EXT2) should be open.
JP4
DIV2
JP5
CLK2
JP6
BCFS
JP7
EXT2
256 384 64fs 32fs
fs
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
MCLK
256fs = 8.192MHz
384fs = 12.288MHz
512fs = 16.384MHz
768fs = 24.576MHz
256fs = 11.2896MHz
384fs = 16.9344MHz
512fs = 22.5792MHz
768fs = 33.8688MHz
256fs = 12.288MHz
384fs = 18.432MHz
512fs = 24.576MHz
768fs = 36.864MHz
256fs = 22.5792MHz
384fs = 33.8688MHz
256fs = 24.576MHz
384fs = 36.864MHz
JP4(DIV2)
256
Open
512
768
256
Open
512
768
256
Open
512
768
256
Open
256
Open
JP5(CLK2)
256
384
256
256
256
384
256
256
256
384
256
256
256
384
256
384
Table 14. Example for Clock setting
3. All clocks are fed through the 10pin port
When using PORT7 (DSP2), nothing should be connected to J2 (EXT2) and PORT6 (DIR2). JP7 (EXT2)
should be short.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
<KM099400>
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2009/03