AKD4122A-A Datasheet, PDF (6/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
(2) Setting for Input port (AK4122A PORT2)
(2-1) Slave mode
1. When using DIR function of AK4114 (U13)
When using PORT6 (DIR2), nothing should be connected to J2 (EXT2) and PORT7 (DSP2). Set JP18
(MCLK2) to the “DIR” when MCLK is supplied to the AK4122A.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• SW3 setting (See Table 3,Table 4,Table 5)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
Name
OCKS
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4114 Master Clock Output Setting
Refer to Table 4
AK4114 Audio Format Setting
Refer to Table 5
Table 3. SW3 setting
Mode
0
1
OCKS
0
1
MCKO1
256fs
512fs
X’tal
256fs
512fs
fs
∼ 96kHz
∼ 48kHz
Default
Table 4. AK4114 MCKO1 setting
Mode
0
1
2
3
Audio I/F Format
16bit, LSB justified
24bit, MSB justified
24bit, I²S Compatible
24bit, LSB justified
DIF2
0
1
1
0
AK4114
DIF1
0
0
0
1
DIF0
0
0
1
1
AK4122A
IDIF1 IDIF0
0
0
0
1
1
0
1
1
Table 5. AK4114 Audio interface format setting
Default
* IDIF1-0 of the AK4122A is set by the register.
<KM099400>
-6-
2009/03