AKD4122A-A Datasheet, PDF (18/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
2. When connecting with the serial interface of UPD, ROHDE & SCHWARZ
When using PORT9 (DSP3), nothing should be connected to PORT10 (DIT3). MCLK is input from J3
(EXT3), BICK LRCK, and DATA are supplied from the AK4122A. Set JP21 (OMCLK) to the “EXT” in order
to supply MCLK to the AK4122A.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
• Clock Setting
MCLK is input from J3 (EXT3). JP10 (EXT3) should be open.
JP8
DIV3
JP9
CLK3
JP10
EXT3
256 384
3. All clocks are fed through the 10pin port
When using PORT9 (DSP3), nothing should be connected to J3 (EXT3) and PORT10 (DIT3). Set JP25 (TST)
to the “OMCK” in order to supply MCLK to the AK4122A. JP10 (EXT3) should be short. MCLK is supplied
to the AK4122A, and BICK, LRCK and DATA are supplied from the AK4122A.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
(5-3) SW1 setting
Set SW1 according to the mode of the AK4122A PORT3.
SW1 No.
1
2
3
Name
M/S2
M/S3
TST4
ON (“H”)
OFF (“L”)
Master Mode
Slave Mode
Master Mode
Slave Mode
Fixed to “L”
Table 26. SW1 setting
Default
L
L
L
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2009/03