AKD4122A-A Datasheet, PDF (4/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
(4) AK4122A PORT1 → SRC → AK4122APORT2
Refer to page 5 for input port setting, and page 11 ∼ 14 for output port setting.
P O RT4
DIR 1
U12
AK 4 1 14
PORT 5
DS P1
AK4122A
BI CK1
LRCK1
SDT I
B ICK 2
LRCK2
SDT IO
MCLK2
U13
A K4 1 14
PORT 7
DS P2
PO RT8
D IT2
J4
EXT1
Divider
J2
E X T2
Figure 6. AK4122A PORT1 → SRC → AK4122A PORT2
(5) AK4122A DIR → SRC → AK4122A PORT2
Refer to page 10 for input port setting, and page 11 ∼ 14 for output port setting.
P O RT3
DI R
J1
RX
AK4122A
RX1
BI CK2
RX2
LRCK2
RX3
S DTI O
RX4
MCLK2
U13
AK 4 1 14
POR T8
DI T2
PO RT7
DS P2
Divider
J2
EXT 2
Figure 7. AK4122A DIR → SRC → KA4122 PORT2
(6) Bypass Mode
Refer to page 5 ∼ 10 for input port setting, and output port setting should be master mode. The bypass mode of the
AK4122A is set by the register.
In bypass mode, the DIT function of the AK4114 can not be used as the output port. 10pin PORT should be used
instead.
Input BICK, LRCK, and DATA are output from the output port side in the bypass mode.
<KM099400>
-4-
2009/03