AKD4122A-A Datasheet, PDF (13/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
(4-2) Master mode
MCLK must be provided in the master mode.
1. When using DIT function of AK4114 (U13)
When using X’tal (X1) and PORT8 (DIT2), nothing should be connected to PORT6 (DIR2) and PORT7
(DSP2). Set JP18 (MCLK2) to the “DIR” when MCLK is supplied to the AK4122A. When MCLK frequency
is changed, the value of X’tal (X1) frequency should be changed according to MCLK frequency.
JP15
SDTIO
JP16
BICK2
JP17
LRCK2
JP18
MCLK2
DIR EXT DIR EXT DIR EXT
• SW3 setting (See Table 15,Table 16,Table 17)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
Name
OCKS
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
AK4114 Master Clock Output Setting
Refer to Table 16
AK4114 Audio Format Setting
Refer to Table 17
Table 15. SW3 setting
Mode
0
1
OCKS
0
1
MCKO1
256fs
512fs
X’tal
256fs
512fs
fs
∼ 96kHz
∼ 48kHz
Table 16. AK4114 MCKO1 setting
Mode
0
1
Audio I/F Format
24bit, MSB justified
24bit, I²S Compatible
DIF2
1
1
AK4114
DIF1
1
1
DIF0
0
1
AK4122A
IDIF1 IDIF0
0
1
1
0
Table 17. AK4114 Audio interface format setting
* IDIF1-0 of the AK4122A is set by the register.
<KM099400>
- 13 -
2009/03