AKD4122A-A Datasheet, PDF (17/37 Pages) Asahi Kasei Microsystems – Evaluation board Rev.0 for AK4122A

[AKD4122A-A]
(5-2) Master mode
MCLK must be provided in the master mode.
1. When using DIT function of AK4114 (U14)
When using X’tal (X2) and PORT10 (DIT3), nothing should be connected to PORT9 (DSP3). Set JP21
(OMCLK) to the “DIT” in order to supply MCLK to the AK4122A. When MCLK frequency is changed, the
value of X’tal (X2) frequency should be changed according to MCLK frequency.
JP19
BICK
JP20
LRCK
JP21
OMCLK
JP25
TST
DIT EXT DIT EXT DIT EXT OMCK TST
• SW4 setting (See Table 23,Table 24,Table 25)
Upper-side is “H” and lower-side is “L”.
SW4 No.
1
2
Name
OCKS
DIF0
ON (“H”)
OFF (“L”)
AK4114 Master Clock Output Setting
Refer to Table 24
AK4114 Audio Format Setting
Refer to Table 25
Table 23. SW4 setting
Mode
0
1
OCKS
0
1
MCKO1
256fs
512fs
X’tal
256fs
512fs
fs
∼ 96kHz
∼ 48kHz
Table 24. AK4114 MCKO1 setting
Mode
0
1
Audio I/F Format
24bit, MSB justified
24bit, I²S Compatible
AK4114
DIF0
0
1
AK4122A
ODIF
0
1
Table 25. AK4114 Audio interface format setting
* ODIF of the AK4122A is set by the register.
<KM099400>
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2009/03