AK4452VN Datasheet, PDF (86/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

Digital Ground
System
Controller
Analog Ground
1
2
3
4
5
6
7
8
[AK4452]
24
23
22
21
20
19
18
17
Figure 78. Ground Layout
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and TVDD
respectively. AVDD are supplied from the analog supply of the system and TVDD is supplied from the digital
supply of the system. When LDOE bit = “1”, TVDD must be powered up before VDD18. Power-up sequences
between AVDD and TVDD, and AVDD and VDD18 are not critical. When LDOE pin = “H”, the internal LDO
outputs 1.8V. Power-up sequence between TVDD and AVDD are not critical. DVSS and AVSS must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be
placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between the VREFH1 pin and the VREFL1 pin sets the analog output range. The
VREFH1 pin is normally connected to AVDD, and the VREFL1 pin is normally connected to AVSS. VREFH1
and VREFL1 should be connected with a 0.1µF ceramic capacitor as near as possible to the pin to eliminate the
effects of high frequency noise. All signals, especially clocks, should be kept away from the VREFH1 and
VREFL1 pins in order to avoid unwanted noise coupling into the AK4452.
Rev. 0.1
- - 86 - -
2014/04