AK4452VN Datasheet, PDF (68/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
(1) Clock Synchronization Sequence when Input Data is “0” for 8192 Cycles Continuously
The DZF pin goes to “H” and the synchronization function becomes enabled when input data is “0” for 8192
time continuously including when the data is attenuated. Figure 65 shows a synchronization sequence.
D/A In
(Digital)
SMUTE
ATT_Level
Attenuation
GD
AOUT
(1)
(1)
-
GD
GD
(4)
DZF pin
Internal Counter
Reset
Internal
Data Reset
(2)
8192/fs
Operation (2)
4~5/fs (3)
(2)
8192/fs
Operation (2)
(5)
Note:
(1) Refer to “■ Output Volume” internal transition time of ATT.
(2) The synchronization function and BICK edge detection function become enabled when all channels
input data are “0” for 8192 times continuously.
(3) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset.
(4) Click noise occurs when the internal counter is reset. This noise is output even if “0” data is input. Mute
the analog output externally if click noise (3) adversely affect system performance.
(5) The internal counter will not be reset when the internal and the external clocks are synchronized even if
the synchronization function is enabled.
Figure 65. Clock Synchronization Sequence with Continuous Zero Data
Rev. 0.1
- - 68 - -
2014/04