AK4452VN Datasheet, PDF (25/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
(Ta=-40  105C; AVDD=3.0  5.5V, TVDD=1.62  1.98V / 3.0  3.6V)
Parameter
Symbol min typ max Unit
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
nsec
CCLK Pulse Width Low
tCCKL
80
nsec
Pulse Width High
tCCKH
80
nsec
CDTI Setup Time
tCDS
40
nsec
CDTI Hold Time
tCDH
40
nsec
CSN “H” Time
tCSW
150
nsec
CSN “” to CCLK “”
tCSS
50
nsec
CCLK “” to CSN “”
tCSH
50
nsec
Control Interface Timing (I²C Bus mode):
SCL Clock Frequency
fSCL
-
400 kHz
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling
(Note 32) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
Capacitive load on bus
Cb
-
- sec
- _sec
- _sec
-
sec
-
sec
-
sec
-
1.0
0.3
sec
sec
-
sec
50 ^nsec
400 ^pF
Power-down & Reset Timing
(Note 33)
PDN Accept Pulse Width
tAPD
150
nsec
PDN Reject Pulse Width
tRPD
30 nsec
Note 32. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 33.The AK4452 can be reset by bringing the PDN pin to “L”.
Note 34. I²C is a trademark of NXP B.V.
Rev. 0.1
- 25 -
2014/04