AK4452VN Datasheet, PDF (67/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
■ Clock Synchronization and BICK Edge Detection Functions
● Clock Synchronization Function
The AK4452 has a function that resets the internal counter to keep a falling edge of the internal FSI clock is in
3/256fs from an edge of the external FSI clock. Clock synchronization function becomes valid when data at all
channels are continuously “0” for 8192 times if SYNCE bit is set to “1” during operation in PCM mode or
when RSTN bit is set to “0”. The operation clock is synchronized to a falling edge of LRCK in PCM mode and
a rising edge of LRCK in I²C mode.
● BCIK Edge Detection Function
When an edge of BICK (digital output) coincides with the end timing of DACSC sampling, the AK4452 delays
the timing of MCLK against digital outputs to prevent analog signal degradation. BCIK edge synchronization
function becomes valid when data at all channels are continuously “0” for 8192 times if the BDET bit is set to
“1” during operation in Daisy Chain mode or when RSTN bit is set to “0”.
The analog output becomes VREFH/2 voltage when RSTN bit = “1” or zero data is detected. Figure 65 shows
a synchronization sequence when the input data is “0” for 8192 times continuously. Figure 66 shows a
synchronization sequence by RSTN bit. Clock synchronization and BICK edge detection functions will be
valid in the same timing.
Rev. 0.1
- - 67 - -
2014/04