AK4452VN Datasheet, PDF (12/91 Pages) Asahi Kasei Microsystems – 115dB 768kHz 32-bit 2ch Premium DAC

[AK4452]
(2) AVDD = 3.3V
(Ta=25°C: TVDD=3.3V, AVDD=3.3V: AVSS= DVSS=0V: VREFH1=AVDD, VREFL1= AVSS:
fs=44.1kHz: BICK=64fs: Signal Frequency=1kHz: 24-bit Input Data: R_L  2k: measurement bandwidth =
20Hz ~ 20kHz: External Circuit: (Figure 79), unless otherwise specified.)
Parameter
min
typ
max Unit
Resolution
32
bit
Dynamic Characteristics
(Note 10)
THD+N
fs=44.1kHz 0dBFS
BW=20kHz 60dBFS
-
-100
-90
dB
-
-48
-
dB
fs=96kHz 0dBFS
-
-97
-
dB
BW=40kHz 60dBFS
-
-45
-
dB
fs=192kHz 0dBFS
-97
-
dB
BW=40kHz 60dBFS
-45
-
dB
BW=80kHz 60dBFS
-42
-
dB
Dynamic Range(60dBFS with A-weighted) (Note 11)
107
111
-
dB
S/N (A-weighted)
(Note 12)
107
111
-
dB
Inter channel Isolation (1kHz)
100
110
-
dB
DC Accuracy
Inter channel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 13)
-
20
-
ppm/°C
Output Voltage
(Note 14)
1.66 1.85 2.04 Vpp
Load Resistance
(Note 15)
2
k
Load Capacitance
(Note 15)
30
pF
Power Supplies
Power Supply Current
Normal operation
(PDN pin = “H”, input opposite phase to each Lch and Rch)
AVDD
-
11(TBD) 15(TBD) mA
TVDD (fs = 44.1kHz)
-
3(TBD) 4(TBD) mA
TVDD (fs = 96kHz)
-
5(TBD) 7(TBD) mA
TVDD (fs = 192kHz)
-
8(TBD) 11(TBD) mA
Power down (PDN pin = “L”)
(Note 16)
AVDD+TVDD
1
100
A
Note 10. Measured by Audio Precision, System Two. Averaging mode.
Note 11. Figure 79 External LPF Circuit Example 1. 100dB for 16-bit data.
Note 12. Figure 79 External LPF Circuit Example 1. S/N does not depend on input data size.
Note 13. The voltage on (VREFH1  VREFL1) is held +5V externally.
Note 14. The full scale voltage when applying a 1kHz sine wave (0dB) in PCM mode, or when applying a
1kHz sine wave (25~75% duty) in DSD mode. Output voltage scales with the voltage of (VREFH1 
VREFL1).
DAC1: AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFH1  VREFL1)/5
Note 15. Regarding Load Resistance, AC load is 2k (min) with a DC cut capacitor (Figure 79). DC load is 2
k (min) without a DC cut capacitor (Figure 79). The load resistance value is with respect to ground.
Analog characteristics are sensitive to capacitive load that is connected to the output pin. Therefore
the capacitive load must be minimized.
Note 16. In the power down mode. All other digital input pins including clock pins (MCLK, BICK and LRCK)
are held DVSS.
Rev. 0.1
- 12 -
2014/04